How OpenAI Used Its Own LLMs to Design Its Jalapeño Chip

TL;DR Highlight

Using LLMs in chip design took OpenAI's Jalapeño from concept to first silicon in under 20 months.

Who Should Read

A backend or infrastructure developer weighing LLM coding agents for domain-specific work like hardware or kernel optimization.

Core Mechanics

Design took under 20 months
- Concept to first silicon took under 20 months.
- First RTL (the code defining the chip's logic) to tape-out (handoff to manufacturing) took nine months.
- The design team averaged fewer than 100 people.
LLMs were pointed at software-like work
- The front-end workflow was built on XLS, an open-source high-level synthesis toolchain originally from Google.
- Designers write in DSLX or C++ and XLS converts it to Verilog.
- OpenAI's Leary said AI was much better at software-looking things.
Kernel tuning took about 40 hours
- On DeepSeek's multi-head latent attention kernel benchmark, performance rose from 0.31% to 88.94% of the theoretical ceiling.
- It took roughly 40 hours.
- Ho says the result is repeatable.
Physical design saved 10% area
- At Hot Chips 2026 they reported a 10% area reduction for matrix multiplication units versus an optimized human baseline.

Community Reactions

Awe at the kernel result
- One commenter with chip bringup experience was amazed by the jump from 0.31% to 88.94% in about 40 hours.
Complaint about vague numbers
- A commenter said it is unclear whether a 3.6x latency reduction means 4.6 vs 1.0 or 3.6 vs 1.0.
- They also questioned which average and which latency were measured.
Critique that nothing new was created
- Some argued AI just recreated an existing chip faster.
- Others said the article describes software development use, not creative design, so the title misleads.
Limits on self-improvement
- One commenter said a 20-month chip turnaround is not breakneck recursive self-improvement.
- They said physical manufacturing and logistics will remain a hard bottleneck.

How to Apply

Have a coding agent do a DSL translation
- Today, pick a config file or schema in your codebase and have an agent write it in a high-level language and convert it.
- Check firsthand the article's point that LLMs do better on software-like input.
Attach a benchmark to your optimization loop
- Define an achieved-versus-theoretical-ceiling metric for the kernel or query you tune.
- Run a loop where the agent edits code and re-measures.
Verify against a human baseline
- Compare AI output numerically against an optimized human implementation.
- Keep an engineer review step for final approval.

Try It

copy & run

# Paste into Claude Code or ChatGPT (simplified version of the article's method: benchmark-driven optimization loop)

You are a performance optimization engineer. Improve the code below, measured as a fraction of the theoretical ceiling.

[Code]
{{code to optimize}}

[Theoretical ceiling]
{{e.g., throughput limited by memory bandwidth}}

[How to run the benchmark]
{{benchmark command}}

Instructions:
1. First, explain how to measure the current achieved fraction.
2. Form three bottleneck hypotheses and write one fix for each.
3. Log measured results in a table after each fix and use them for the next one.

Next step: keep only the most effective fix and review it by hand.

Terminology

RTLCode that describes a chip's logic as data flow between registers. It is like the source code of a chip.

tape-outThe point where a finished design is sent to manufacturing. Like the release just before production.

XLSAn open-source high-level synthesis toolchain originally from Google. It converts software-language designs into Verilog.

High-level synthesis (HLS)Automation that lets engineers design chips in a familiar programming environment. Like a compiler that generates hardware code.

Front end / back end designFront end spans concept through RTL and verification. Back end covers routing, clock and power specs, and handoff to the foundry.