Can AI design circuit boards yet?

Who Should Read

A developer who wants LLM agents to design electronics and needs a way to verify the results.

Core Mechanics

• Circuits as code, not GUI
  • EEBench uses atopile, a declarative circuit language.
  • Agents work directly on components, connections and electrical constraints instead of clicks and coordinates.
  • They can edit, build, simulate and inspect failures inside the project.
• Builds pass, circuits still fail
  • The energy-meter task must keep a rail above 3.0V for 20 ms after power loss.
  • A submission with 22 µF had only 11.4 µF effective capacitance at 4.7 V bias.
  • The requirement was 545 µF and the rail fell below 3 V after 0.85 ms.
• Grading is fully deterministic
  • The harness builds the design, creates the circuit graph and BOM, and runs SPICE simulations and checks.
  • Each requirement yields a measurement with a limit.
  • Cost efficiency only counts once the circuit works.
• Real parts force real trade-offs
  • Datasheet specs are carried into the SPICE models and tested at tolerance corners.

Community Reactions

• Veteran PCB designer had Fable design an LED earring
  • Two mistakes: missed through holes on the coin cell holder footprint and a too-small center pad.
  • It worked after a JLC part swap and some solder, and cost about $50 on a Max plan over 6 days.
• Layout and complex analog/RF still weak, some say
  • Simple schematics were decent but PCB layout was terrible every time.
  • They advised feeding datasheets and errata.
• Use an LLM to cross-check netlist and BOM
  • Commenters said it checks pins, polarity, part specs and bus termination against datasheets.
• Doubts about the benchmark
  • One commenter noted the leaderboard looks like a single run per task and model, so it may be noisy.
  • Another said unclear methodology may mean it tests unstated constraints.
• Generate boards with deterministic scripts
  • One commenter had Claude write deterministic scripts to create boards.

How to Apply

• Have an LLM review your netlist and BOM
  • Paste your current board's netlist, BOM and datasheets into an LLM.
  • Ask for a table of pin, polarity and spec issues.
• Use simulation-based grading for hardware agents
  • Define success by SPICE measurements against limits, not by a successful build.
  • Include worst-case tolerance corners.
• Use code-based design tools instead of GUIs
  • Choose a declarative tool like atopile for agent-driven boards.
  • Wrap build, simulate and inspect failures in one loop.
• Feed failure logs back into retries
  • Record which voltage or corner broke its limit and add it to the next prompt.
  • Also record cost overruns.

Try It

# Paste into Claude or ChatGPT (simplified version of the EEBench approach)

You are an electronics design reviewer. Review the design below using real parts, not ideal values.

[Requirements]
{{requirements: e.g., rail stays above 3.0V for 20 ms after 5V loss}}

[Netlist/BOM]
{{netlist and BOM}}

[Datasheet/errata]
{{datasheet excerpts}}

Answer in this order.
1. Make a table of the value to measure and the limit for each requirement.
2. Calculate pass/fail under worst cases such as tolerance and DC-bias capacitance loss.
3. List failing items and reasons.
4. Propose fixes considering cost and size.

Next step: ask it to turn the fix into ngspice tests.

Terminology

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Related Resources

• https://eebench.org/blog/can-ai-design-circuit-boards-yet/
• https://eebench.org/
• https://eebench.org/methodology.html
• https://www.jitx.com/
• https://github.com/JITx-Inc/jitx-skills
• https://github.com/itomato/NeXTBus-Dev-Board