AI Compute Extensions (ACE) Specification

Who Should Read

Backend/infra developers curious about hardware acceleration support for running LLM inference on CPUs

Core Mechanics

• ACE is an x86 AI compute extension
  • It is a spec document from the x86 Ecosystem Advisory Group.
  • It first targets matrix multiplication kernels and reduced precision data formats.
• New register state is added
  • It adds tile registers and block scale registers.
  • It also defines state and operations for system management.
• It is built to work with AVX
  • Some operations take AVX register input and compute on tile register state.
  • Data move operations transfer data between AVX registers and ACE state.
• Format conversion ops are included
  • Dedicated format convert operations are provided besides matrix acceleration.
  • They sit under the AVX10 framework.

Community Reactions

• Question on difference from AVX/SSE
  • One commenter asked how this differs from SSE/AVX instructions already on most x64 machines.
• Opinion that AVX512 availability matters
  • One commenter said AVX512 is missing on most new CPUs, so ACE may be server-only for a couple of years.

How to Apply

• Check AVX support on your servers
  • Run lscpu on an inference server today and look for avx512 and avx10 flags.
  • Record the result in a table of your deployment instance types.
• Hold CPU inference decisions and just track the spec
  • The source only defines the spec and gives no performance numbers.
  • Benchmark once real CPU support ships.

Try It

# Paste into a Linux shell: list AVX-related CPU flags

grep -o -E 'avx[0-9a-z_]*' /proc/cpuinfo | sort -u

Terminology

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Related Resources

• https://x86ecosystem.org/resource/ai-compute-extensions-ace-specification/